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74F569 4-Bit Bidirectional Counter with 3-STATE Outputs
April 1988 Revised August 1999
74F569 4-Bit Bidirectional Counter with 3-STATE Outputs
General Description
The 74F569 is a fully synchronous, reversible counter with 3-STATE outputs. The 74F569 is a binary counter, featuring preset capability for programmable operation, carry lookahead for easy cascading, and a U/D input to control the direction of counting. For maximum flexibility there are both synchronous and master asynchronous reset inputs as well as both Clocked Carry (CC) and Terminal Count (TC) outputs. All state changes except Master Reset are initiated by the rising edge of the clock. A HIGH signal on the Output Enable (OE) input forces the output buffers into the high impedance state but does not prevent counting, resetting or parallel loading.
Features
s Synchronous counting and loading s Lookahead carry capability for easy cascading s Preset capability for programmable operation s 3-STATE outputs for bus organized systems
Ordering Code:
Order Number 74F569SC 74F569SJ 74F569PC Package Number M20B M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
FAST(R) is a registered trademark of Fairchild Semiconductor Corporation.
(c) 1999 Fairchild Semiconductor Corporation
DS009565
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74F569
Unit Loading/Fan Out
Pin Names P0-P3 CEP CET CP PE U/D OE MR SR O0-O3 TC CC Description Parallel Data Inputs Count Enable Parallel Input (Active LOW) Count Enable Trickle Input (Active LOW) Clock Pulse Input (Active Rising Edge) Parallel Enable Input (Active LOW) Up/Down Count Control Input Output Enable Input (Active LOW) Master Reset Input (Active LOW) Synchronous Reset Input (Active LOW) 3-STATE Parallel Data Outputs Terminal Count Output (Active LOW) Clocked Carry Output (Active LOW) U.L. HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 150/40(33.3) 50/33.3 50/33.3 Input IIH/IIL Output IOH/IOL 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-1.2 mA 20 A/-0.6 mA 20 A/-1.2 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA -3 mA/24 mA (20 mA) -1 mA/20 mA -1 mA/20 mA
Functional Description
The 74F569 counts in the modulo-16 binary sequence. From state 15 it will increment to state 0 in the Up mode; in the Down mode it will decrement from 0 to 15. The clock inputs of all flip-flops are driven in parallel through a clock buffer. All state changes (except due to Master Reset) occurs synchronously with the LOW-to-HIGH transition of the Clock Pulse (CP) input signal. The circuits have five fundamental modes of operation, in order of precedence: asynchronous reset, synchronous reset, parallel load, count and hold. Five control inputs-- Master Reset (MR), Synchronous Reset (SR), Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle CET)--plus the Up/Down (U/D) input, determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces the flip-flop Q outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows the Q outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With MR, SR and PE HIGH, CEP and CET permit counting when both are LOW. Conversely, a HIGH signal on either CEP or CET inhibits counting. The 74F569 uses edge-triggered flip-flops and changing the SR, PE, CEP, CET or U/D inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. Two types of outputs are provided as overflow/underflow indicators. The Terminal Count (TC) output is normally HIGH and goes LOW providing CET is LOW, when the counter reaches zero in the Down mode, or reaches maximum (15) in the Up mode. TC will then remain LOW until a state change occurs, whether by counting or presetting, or until U/D or CET is changed. To implement synchronous multistage counters, the connections between the TC output and the CEP and CET inputs can provide either slow or fast carry propagation. Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle takes 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. For such applications, the Clocked Carry (CC) output is provided. The CC output is normally HIGH. When CEP, CET, and TC are LOW, the CC output will go LOW when the clock next goes LOW and will stay LOW until the clock goes HIGH again, as shown in the CC Truth Table. When the Output Enable (OE) is LOW, the parallel data outputs O0-O3 are active and follow the flip-flop Q outputs. A HIGH signal on OE forces O0-O3 to the High Z state but does not prevent counting, loading or resetting.
Logic Equations
Count Enable = CEP * CET * PE Up: TC = Q0 * Q1 * Q2 * Q3 * (Up) * CET Down: TC = Q0 * Q1 * Q2 * Q3 * (Down) * CET
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74F569
CC Truth Table
Inputs SR L X X X X H PE X L X X X H CEP CET X X H X X L X X X H X L TC (Note 1) X X X X H L CP X X X X X Output CC H H H H H
Mode Select Table
Inputs MR L H H H H H H SR X L H H H H H PE X X L H H H H CEP CET U/D X X X H X L L X X X X H L L X X X X X H L Operating Mode Asynchronous Reset Synchronous Reset Parallel Load Hold Hold Count Up Count Down
H = HIGH Voltage Level L = LOW Voltage Level
Note 1: TC is generated internally

X = Immaterial = HIGH-to-LOW-to-HIGH Clock Transition

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
FIGURE 1. Multistage Counter with Ripple Carry
FIGURE 2. Multistage Counter with Lookahead Carry
State Diagram
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74F569
Logic Diagram
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74F569
Absolute Maximum Ratings(Note 2)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +175C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V
Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 10% VCC 10% VCC 5% VCC 5% VCC VOL IIH IBVI ICEX VID IOD IIL Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current 4.75 3.75 -0.6 -1.2 IOZH IOZL IOS IZZ ICCH ICCL ICCZ Output Leakage Current Output Leakage Current Output Short-Circuit Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current 45 45 45 -60 50 -50 -150 500 67 67 67 10% VCC 10% VCC 2.5 2.4 2.7 2.7 0.5 V 0.5 5.0 7.0 A A A V A mA mA A A mA A mA mA mA Max Max Min V Min Min 2.0 0.8 -1.2 Typ Max Units V V V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA (TC, CC, On) IOH = -3 mA (On) IOH = -1 mA (TC, CC, On) IOH = -3 mA (On) IOL = 20 mA (TC, CC) IOL = 24 mA (On) VIN = 2.7V VIN = 7.0V VOUT = VCC (TC, CC, On) IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (Pn, CEP, CP, U/D, OE, MR, SR) VIN = 0.5V (PE, CET) VOUT = 2.7V (On) VOUT = 0.5V (On) VOUT = 0V (TC, CC, On) VOUT = 5.25V (On) VO = HIGH VO = LOW VO = HIGH Z
50
Max 0.0 0.0 Max Max Max Max Max 0.0V Max Max Max
5
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74F569
AC Electrical Characteristics
TA = +25C Symbol Parameter Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay CP to On (PE HIGH or LOW) Propagation Delay CP to TC Propagation Delay CET to TC Propagation Delay U/D to TC Propagation Delay CP to CC Propagation Delay CEP, CET to CC Propagation Delay MR to On Output Enable Time OE to On Output Disable Time OE to On 90 3.0 4.0 5.5 4.0 2.5 2.5 3.5 4.0 2.5 2.0 2.5 4.0 5.0 2.5 3.0 1.5 2.0 6.5 9.0 12.0 8.5 4.5 6.0 8.5 8.0 5.5 4.5 5.0 8.5 10.0 5.5 6.0 5.0 4.5 8.5 11.5 15.5 12.5 6.5 11.0 11.5 12.0 7.0 6.0 6.5 11.0 13.0 8.0 9.0 7.0 6.0 VCC = +5.0V CL = 50 pF Typ Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 70 3.0 4.0 5.5 4.0 2.5 2.5 3.5 4.0 2.0 2.0 2.0 4.0 5.0 2.5 3.0 1.5 2.0 9.5 13.0 17.5 13.0 7.0 12.0 12.5 13.0 8.0 7.0 7.5 12.5 14.5 8.5 10.0 8.0 7.0 ns Max MHz ns Units
ns
ns
ns
ns
ns
ns
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74F569
AC Operating Requirements
TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) tW(L) tREC Setup Time, HIGH or LOW Pn to CP Hold Time, HIGH or LOW Pn to CP Setup Time, HIGH or LOW CEP or CET to CP Hold Time, HIGH or LOW CEP or CET to CP Setup Time, HIGH or LOW PE to CP Hold Time, HIGH or LOW PE to CP Setup Time, HIGH or LOW U/D to CP Hold Time, HIGH or LOW U/D to CP Setup Time, HIGH or LOW SR to CP Hold Time, HIGH or LOW SR to CP CP Pulse Width, HIGH or LOW MR Pulse Width, LOW MR Recovery Time 4.0 4.0 3.0 3.0 7.0 5.0 0 0.5 8.0 8.0 0.0 0 11.0 7.0 0 0 10.5 8.5 0 0 4.0 7.0 4.5 6.0 Max TA = 0C to +70C VCC = +5.0V Min 4.5 4.5 3.5 3.5 8.0 6.5 0 0.5 9.0 9.0 1.0 0 12.5 8.5 0 0 11.0 9.5 0 0 4.5 8.0 6.0 8.0 ns ns ns ns ns ns ns ns Max Units
ns
7
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74F569
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74F569 4-Bit Bidirectional Counter with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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